
`timescale 1 ns / 1 ps

module Master_axi_stream_v1_0 #
	   (
		   // Users to add parameters here

		   // User parameters ends
		   // Do not modify the parameters beyond this line


		   // Parameters of Axi Master Bus Interface M00_AXIS
		   parameter integer C_M00_AXIS_TDATA_WIDTH	= 32,
		   parameter integer C_M00_AXIS_START_COUNT	= 32
	   )
	   (
		   // Users to add ports here
		   input	i_Clk_sys,
		   input	i_Rst_n,

		   input	Data_valid_in,
		   input[ 15: 0 ] FPA_data_in,
		   input	Filter_enable,
		   input[ 4: 0 ] Filter_threshold,
		   input[ 15: 0 ] Filter_data,
		   // User ports ends
		   // Do not modify the ports beyond this line


		   // Ports of Axi Master Bus Interface M00_AXIS
		   input wire m00_axis_aclk,
		   input wire m00_axis_aresetn,
		   output wire m00_axis_tvalid,
		   output wire [ C_M00_AXIS_TDATA_WIDTH - 1 : 0 ] m00_axis_tdata,
		   output wire [ ( C_M00_AXIS_TDATA_WIDTH / 8 ) - 1 : 0 ] m00_axis_tstrb,
		   output wire m00_axis_tlast,
		   input wire m00_axis_tready
	   );

parameter CNT_50HZ = 720000 ;//@36MHZ CNT_50HZ*1000/36=20000000
parameter CNT_HOR = 640 ;//
parameter CNT_VER = 480 ;//
reg field_sync;
reg field_rst;
reg[31:0] cnt_field_sync;
reg[9:0] cnt_hor;
reg[9:0] cnt_ver;
reg h_valid;
reg v_valid;
wire [13:0] axi_data_in;

/*****************************************fidle_sync***********************************************/
// Instantiation of Axi Bus Interface M00_AXIS
Master_axi_stream_v1_0_M00_AXIS # (
									.C_M_AXIS_TDATA_WIDTH( C_M00_AXIS_TDATA_WIDTH ),
									.C_M_START_COUNT( C_M00_AXIS_START_COUNT )
								) Master_axi_stream_v1_0_M00_AXIS_inst (
									.i_Clk( i_Clk_sys ),
									.i_Data( axi_data_in ),
									.i_Dvld( axi_d_vld ),
									.i_Frame_rst( field_rst ),

									.M_AXIS_ACLK( m00_axis_aclk ),
									.M_AXIS_ARESETN( m00_axis_aresetn ),
									.M_AXIS_TVALID( m00_axis_tvalid ),
									.M_AXIS_TDATA( m00_axis_tdata ),
									.M_AXIS_TSTRB( m00_axis_tstrb ),
									.M_AXIS_TLAST( m00_axis_tlast ),
									.M_AXIS_TREADY( m00_axis_tready )
								);

// Add user logic here


always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		cnt_field_sync <= 32'd0;
	end
	else if ( cnt_field_sync == CNT_50HZ-1 ) begin
		cnt_field_sync <= 32'd0;
	end
	else begin
		cnt_field_sync <= cnt_field_sync + 32'd1;
	end
end
always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		field_sync <= 1'd0;
	end
	else if ( cnt_field_sync == CNT_50HZ-1 ) begin
		field_sync <= ~field_sync;
	end
	else begin
		field_sync <= field_sync ;
	end
end
always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		field_rst <= 1'd0;
	end
	else if ( cnt_field_sync == CNT_50HZ-1 ) begin
		field_rst <= 1'b1;
	end
	else begin
		field_rst <= 1'b0 ;
	end
end
always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		cnt_hor <= 10'd0;
	end
	else if ( field_rst ) begin
		cnt_hor <= 10'd0;
	end
	else if ( cnt_hor == CNT_HOR+200-1 ) begin
		cnt_hor <= 10'd0;
	end
	else begin
		cnt_hor <= cnt_hor + 10'd1;
	end
end
// assign end_of_line = ( cnt_hor == CNT_HOR+200-1 )
always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		cnt_ver <= 10'd0;
	end
	else if ( field_rst ) begin
		cnt_ver <= 10'd0;
	end
	else if ( cnt_ver == CNT_VER+20-1 ) begin
		cnt_ver <= cnt_ver;
	end
	else if(cnt_hor == CNT_HOR+200-1)begin
		cnt_ver <= cnt_ver + 10'd1;
	end
	else begin
		cnt_ver <= cnt_ver;
	end
end
always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		v_valid <= 1'd0;
	end
	else if(cnt_ver >= 10 && cnt_ver < CNT_VER+ 10 )begin
		v_valid <= 1'd1;
	end
	else begin
		v_valid <= 1'd0;
	end
end

always@( posedge i_Clk_sys ) begin
	if ( !i_Rst_n ) begin
		h_valid <= 1'd0;
	end
	else if(v_valid && cnt_hor >= 50 && cnt_hor < CNT_HOR+ 50 )begin
		h_valid <= 1'd1;
	end
	else begin
		h_valid <= 1'd0;
	end
end
assign axi_data_in= (h_valid && v_valid) ? cnt_hor : 14'd0;
assign axi_d_vld= (h_valid && v_valid) ;
// User logic ends

endmodule
